In mathematical operation, multiplication and division are one of the major functions to perform. The multiplication function is customarily achieved by multiple additions in digital computers. Such a procedure involve large number of operations and require a great deal of hardware.
One of the areas where multiplication is indispensible is in signal processing, where the products of two variables are summed. Recent development in charge coupled devices makes it feasible to sum a large number of quantities simultaneously. However, for correlation and convolution, the quantities must be multiplied before the products are summed. Thus, an analog multiplier is needed for such applications.
In a charge-coupled device the signals which should be multiplied are derived from a floating gate. The equivalent circuit for such a floating gate is a capacitor, which has high impedance. The voltages derived from the floating gates should be applied to a high impedance multiplier so as to preserve the amplitude.
A conventional conductance multiplier operates a MOSFET near the origin of its V-I characteristics with one multiplicant appearing as gate voltage and the other multiplicant appearing as drain voltage. The drawback of this kind of circuit is that the drain voltage must be fed to the low drain impedance. What is needed is a multiplier which can be fed from a high impedance source.